...or UVVM. Knowledge of the Linux operating system for embedded devices. Proficiency in embedded software programming C/C++. Verilog and System Verilog. Proficiency in Python programming. Background in signal processing. Benefits A dynamic and... 
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3Brain AG

Freienbach SZ
Vor 20 Tagen
 ...design, and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting; Python scripting is a plus Bachelor Degree minimum... 
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CDI

Kandou Bus SA

Kanton Waadt
Vor 14 Tagen
 ...chanes outilles des familles XIilinx Microsemi Lattice et Intel/Altera. galement vous tes oprationnel(le) sur un langage tel que VHDL VERILOG et System Verilog. La connaissance de lUVM est un plus. Votre niveau danglais vous permet de comprendre une documentation... 
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TheWiseSeeker

Cully, Bourg-en-Lavaux, VD
Vor einem Monat
 ...Digital frontend to backend implementation: concept definition, specification, requirement mapping, architectural design, RTL in Verilog / System Verilog, synthesis including test insertion, timing analysis, place route, I/R-drop analysis, silicon sign-off, ATPG Experience... 
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Albelissa Technical Recruiting

Rapperswil-Jona SG
vor 2 Monaten
 ...Schwerpunkt Ihres Studiums lag im Bereich der Softwareentwicklung und Sie konnten sich dabei ein gutes Fachwissen in C/C++ und VHDL/Verilog für die Entwicklung von Embedded-Systemen aneignen. Diese Stelle eignet sich sowohl für Berufserfahrene wie auch für... 
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Manexperts

Zürich ZH
vor 2 Monaten
 ...Engineering or similar A proven background working as a Digital IC Design Engineer, with solid hands-on skills in RTL design - Verilog / SystemVerilog (circa 5-10+ years' experience), and digital-analog integration A good handle on ASIC Verification activities... 
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IC Resources

Neuenburg NE
Vor 14 Tagen
 ...digital design verification, using standardized methodologies, i.e. UVM Experience in simulating mixed signal designs with real-number Verilog behavioural models is highly desirable Familiarity with SerDes is highly desirable Experience with SystemVerilog Assertions (SVA)... 
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Kandou Bus SA

Kanton Waadt
Vor 2 Tagen
 ...Embedded software application) verification/simulation testing/debugging qualification and documentation. Experience using VHDL Verilog or System Verilog for Altera/Microsemi devices and synthesis/simulation tools. Experience with NIOS and ARM is a plus. Familiarity... 
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Vision Markets - Your global growth in Machine Vision

Wil SG
Vor einem Monat
 .../or knowledge Experience in the design of electronics based on field programmable logic-based devices (FPGA);Knowledge of VHDL/ Verilog/ System Verilogm, Xilinx VivadoKnowledge of DevOps tools such as: Gitlab CI/CD, automated hardware testsFluent in English, the ability... 
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European Council for Nuclear Research

Genf GE
vor 2 Monaten
 ...for the mitigation of radiation effects (SEE and TID) in digital CMOS circuits; Experience in the development of synthesizable Verilog RTL code, design implementation (RTL to GDS), physical and functional verification of mixed-signal ASICs; Experience with the use... 
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CERN

Genf GE
Vor 29 Tagen
 ...accelerators.Knowledge of hardware accelerators; preferably with experience in GPU coding in CUDA or FPGA firmware development in HLS, System Verilog, or VHDL as a plus.Competence with developing track / muon reconstruction software and / or developing, training and evaluating... 
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European Council for Nuclear Research

Genf GE
Vor einem Monat
 ...Manufacturing (PVT corners, reliability)Layout Parameter Extraction (LPE) simulationsIR drop /EM analysisAnalog behavioral modeling (Verilog-A/Verilog-AMS)Laboratory experience in silicon bring-up and validationScripting language (Python, TCL, Shell) Join us in this... 
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European Council for Nuclear Research

Genf GE
vor 2 Monaten
 ...protection mechanisms against Single Event Effects, HDL simulation, timing and placement constraints, and verification tools (eg System Verilog/UVM).Commissioning, maintenance and operation of readout systems and data-links in HEP experiments.Software scripting and... 
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European Council for Nuclear Research

Genf GE
vor 2 Monaten
 ...experience: Process-Voltage-Temperature (PVT) corners, Layout Parameter Extraction (LPE) simulationsAnalog behavioural modelling (Verilog-A/Verilog-AMS)IRdrop/EM analysisScripting language (Python, TCL, Shell)Hardware description language (Verilog, SystemVerilog)Laboratory... 
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European Council for Nuclear Research

Genf GE
vor 2 Monaten