Senior Analog IC Layout Engineer - Hybrid, High-Speed
IC Resources
IC Resources is seeking a Senior IC Layout Engineer for a growing semiconductor team in Lausanne. The role features a hybrid working model with three days per week in the office and a focus on custom analog layout and physical verification.You will handle layout and verification for high-speed designs, including multi-gigabit SerDes and memory interfaces, and may take ownership of broader chip layout activities as you progress. #J-18808-Ljbffr
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